The present invention relates to the field of electronics, and, more particularly, to a frequency multiplying circuit.
In digital processing circuitry, it is often necessary to double the frequency of a clock signal, or in general, to double the frequency of a digital signal having a 50% duty cycle. It is important to ensure that the output signal that has been doubled in frequency retains a 50% duty cycle. This output signal is often used to derive an internal frequency of four times the frequency of the input signal, and any deviation from the 50% duty cycle could induce an error in the higher frequency signals derived therefrom.
A circuit used for doubling the frequency of an input signal with a 50% duty cycle is shown in FIG. 1. The circuit uses an XNOR or an XOR gate having a first input coupled to the digital input signal CLK. The second input receives a replica of the input signal CLK delayed by a quarter of a time period using a delay line. The delay line includes a cascade of three identical inverters, and a capacitor connected between the coupling node of the output of the first inverter to the input of the second inverter and ground. The delay introduced by the delay line must be a quarter of the period time of the input signal CLK.
Referring to FIG. 2, waveforms of the signals indicated in FIG. 1 are illustrated. These signals are the output signal of the XNOR gate and the corresponding input signals. The output signal is at a high logic level. Increasing frequencies of the processed digital signals and stricter precision requirements for sampling frequencies make it difficult to ensure that the delay times of the components of the delay line of the circuit in FIG. 1 match to provide the required quarter of a time period delay.
The above described difficulties of the prior art circuit are overcome by a circuit according to the present invention while providing a 50% duty cycle of the output signal.
The circuit includes a comparator for sensing when a voltage on a capacitor charged with a constant current during a phase of the input signal of 50% duty cycle reaches a half of its full charge swing. Half of the voltage of the charging process of the capacitor is accomplished during one phase of the 50% duty cycle of the input signal. Since this voltage is reached at half the time interval of the charging phase, the comparator output switches at substantially a quarter of the period of the input signal.
Instead of using a resistive voltage divider of the voltage present on the charging capacitor, the latter may be made up of two capacitors of identical value connected in series. The comparator senses the voltage present on one of the two capacitors in series.
A constant current generator and a switch controlled by the input signal and by its inverse signal, or by functionally equivalent control signals, operatively provide for a linear charging of the capacitor or capacitors in series during a first half period of the input signal. The constant current generator and switch operatively provide for a complete discharge of the capacitor or of the capacitors in series during the following half period of the input signal. Also, the discharging may be after the switching of the half-swing sensing comparator.
The output gate may either be an XNOR or an XOR gate. The capacitor charging and discharging circuit and the relative comparator may be duplicated according to a common dual architecture of digital circuitry.